As is well known in the art of digital computers, a computer bus is the communications path used to connect the separate electronic devices of which a computer is comprised. It is, in effect, the highway on which data and commands travel between such devices. The separate devices connected by such a bus normally include one or more processors, which perform the basic computation of the system; memory boards, which provide relatively high speed storage of data and commands for use by the processors; and I/O devices, such as disk and tape drives for providing slower but much larger memory, and such as devices for communicating with other computers or with user terminals. Usually the bus is comprised of a plurality of parallel wires, and the separate electronic devices each include a printed circuit board on which electronic components are mounted. The bus normally contains a series of connector sockets attached to it. Each such connector is configured so that when an edge of a board designed for use with the bus is plugged into it, edge connectors on the board will be connected though contacts in the connector to their corresponding wires on the bus, electronically connecting wires on the board to the bus.
As used in its narrow sense, the phrase "computer bus" can refer just to a physical communications path of the type described above. Unless indicated otherwise, this is the meaning in which the word "bus" is used in the patent claims that follow. But in a broader sense, a "computer bus" is defined by much more than just the wires of which it is made. It is also defined by what is known as a bus protocol, or bus architecture. A bus protocol includes a complex set of pre-defined rules about how the wires of its bus are to be used. It specifies what information is supposed to be transmitted on which wires, by which devices, at which times. It specifies how the different devices on the bus are to respond to, and interpret, information on specific wires of the bus at given times. It specifies how the different devices on the bus are to determine which of them gets to use the bus next. And it specifies how various transactions between such devices are to be performed. A bus protocol's rules allow different devices to use the bus without interfering with each other, and make it possible for different devices to communicate with each other in a manner which is mutually understood.
Thus, it can be seen that when a given device is connected to a computer bus, it must either obey the bus protocol of the other devices on the bus or, at the least, behave in a manner that is functionally compatible with the protocol of other devices on the bus. This is necessary to enable the given device to properly communicate with such other devices, and to prevent unwanted interference between devices. Traditionally, all bus devices designed for use on a given bus seek to obey all the rules of a common protocol associated with that bus, so as to prevent communication problems. Unfortunately, however, no bus protocol can be optimal for all purposes. Therefore, the traditional requirement that all bus devices connected to a given bus must obey the protocol associated with that bus can be limiting.
As is explained below in greater detail, the preferred embodiment of the present invention relates to bus devices which use the COM, or Clearpoint Open Market, bus communications protocol. This protocol is unusual, in that it is designed for use on buses which contain one or more devices which obey another bus protocol. In the case of the COM protocol, the protocol with which it is designed to be used is the so-called BI, or Backplane Interconnect, bus protocol. "BI" is a trademark of Digital Equipment Corporation, 146 Main Street, Maynard, Mass., the company which manufactures several different models of computers which use the BI bus and bus protocol.
The BI protocol probably constitutes the most relevant prior art to the COM protocol. The BI protocol is explained in detail in the following five U.S. Pat. Nos.:
U.S. Pat. No. 4,661,905, entitled "Bus-Control Mechanism", issued to Frank C. Bomba et al. on Apr. 28, 1987;
U.S. Pat. No. 4,706,190, entitled "Retry Mechanism For Releasing Control Of A Communications Path A In Digital Computer System", issued to Frank C. Bomba on Nov. 10, 1987;
U.S. Pat. No. 4,763,249, entitled "Bus Device For Use In A Computer System Having A Synchronous Bus", issued to Frank C. Bomba et al. on Aug. 9, 1988;
U.S. Pat. No. 4,769,768, entitled "Method And Apparatus For Requesting Service Of Interrupts By Selected Number Of Processors", issued to Frank C. Bomba et al. on Sept. 6, 1988; and
U.S. Pat. No. 4,787,033, entitled "Arbitration Mechanism For Assigning Control Of a Communications Path In A Digital Computer System", issued to Frank C. Bomba et al. on Nov. 22, 1988.
Collectively these five patents are referred to herein as the "BI patents", and the BI patents are hereby incorporated herein by reference. Because of the BI protocol's relevance to the present invention, a detailed description of that protocol, derived from the BI patents, is set forth below in the Detailed Description Of Preferred Embodiments.
The preferred embodiment of the present invention also relates to bus interface chips of the type designed to be part of a bus device and to connect the wires of the computer's bus with the wires of an internal bus, or collection of wires, contained on such a bus device. Commonly such interface chips contain much of the logic which enables the bus devices of which they are part to obey a given bus protocol. Bus interface chips of this general description are well known in the computing arts. For example, most bus devices which use the BI bus protocol use a bus interface chip called the BIIC, or BI Interface Chip, which is sold by Digital Equipment Corporation.